▶ IBM has unveiled progress on Starling, its fault-tolerant quantum computer targeted for operation in 2029.
▶ Starling is designed to perform 100 million quantum operations using 200 logical qubits.
▶ The biggest change is in the processor design. Reducing the number of connections per qubit from six to five has improved the logical error rate by a factor of 20 to 100.
▶ IBM has also cut the number of Josephson junctions—the key components in superconducting circuits—from about 5,000 to 2,000, a reduction of 60%.
IBM has disclosed interim results in developing Starling, its fault-tolerant quantum computer targeted for operation in 2029. In a research blog post this month, the company said it had made technical progress in six areas: device physics and quantum processors, error-correction decoders, intermodule connections, cryogenic cooling and wiring, and control electronics.
The key is a design that can scale up quantum computers while reducing errors. IBM has improved the qubit connection structure and cut the number of key components by 60%. It has also made progress in experiments linking separate quantum processors.
Starling is designed to perform 100 million quantum operations using 200 logical qubits. IBM is improving individual components and processor designs while retaining the system’s basic architecture. The company said the results confirmed that its chosen development direction is sound.
The biggest challenge for quantum computers: error correction
Quantum computers process information differently from conventional computers. While conventional computers use bits that represent information as 0s and 1s, quantum computers use qubits, which can take advantage of quantum-mechanical superposition.
The problem is that qubits are extremely sensitive to their surroundings. Even small disturbances, such as heat or electromagnetic noise, can change their quantum states and cause computational errors. Errors can also accumulate as computations get longer. Reliable execution of complex calculations requires technology to detect and correct errors.
One way to address this is with a “logical qubit.” A logical qubit is an information unit that distributes quantum information across multiple physical qubits so that errors can be detected and corrected. This helps protect the overall information even if an individual qubit develops an error.
The technical challenge is how many physical qubits are needed. With conventional error-correction methods, it can take hundreds or more physical qubits to implement one stable logical qubit. IBM aims to address this with a quantum low-density parity-check (qLDPC) code it announced in the journal Nature in 2024.
According to IBM, the qLDPC architecture planned for Starling can reduce physical-qubit requirements to about one-tenth those of existing approaches at the same logical error rate. In 2025, IBM also unveiled a modular design for implementing the code in actual hardware. It combines quantum memory and a logical processing unit (LPU) in a single module, with multiple modules connected to one another.
60% fewer key components, with chip yield projected to quadruple
The most notable result in the announcement was an improved quantum processor design. IBM refined its qLDPC error-correction code, reducing the number of connections required per qubit from six to five. The connection structure is simpler, yet the company said the logical error rate is 20 to 100 times lower than before.
IBM has also significantly reduced the number of Josephson junctions used in superconducting circuits. A Josephson junction consists of a thin insulating layer between two superconductors. It plays an important role in enabling and controlling the quantum states of superconducting qubits.
By improving its coupler design, IBM reduced the number of Josephson junctions needed in a processor from about 5,000 to 2,000—a 60% decrease. Fewer components could lead to improved manufacturing yields.
IBM estimated the share of fully functioning chips based on an assumed 99.95% probability that each Josephson junction works properly. With the existing design of 5,000 junctions, about one in 12 chips was projected to work fully. With the number of junctions reduced to 2,000, the estimate rose to about one in three. In other words, the projected share of fully functioning chips increases from about 8.3% to 33.3%.
These figures are projections based on the yield of individual junctions, not actual mass-production results. IBM also extended the c-coupler, which connects qubits that are far apart on a chip, to 20 millimeters. This eases design constraints that require qubits and their connecting components to be packed into a limited space.
The number of wiring layers carrying the couplers has increased from two to three, with plans to expand to four or more. IBM has incorporated these results into a redesigned modular quantum processor. The new design is intended to reduce manufacturing risks and raise production yields.
Test chip performance improves, but error rates remain a challenge
IBM also released measurement results for Loon, a test quantum processor it unveiled last year. Loon is a chip designed to validate the qubit initialization circuits and long-range connections needed for qLDPC error correction.
Measurements showed a T1 relaxation time—the time it takes a qubit to lose energy—of about 200 microseconds. The median gate error rate was about 0.3%. Starling’s target performance is a T1 time in the millisecond range and a gate error rate in the low 0.01% range.
IBM said it has previously lowered gate error rates to as little as 0.04% on its Heron and Nighthawk processors. Work is continuing to improve Loon’s measured performance to Starling’s target level.
Results were more encouraging for the chip’s internal connections. The quality factor (Q) of c-coupler resonators exceeded 10 million. The quality factor indicates how little energy a resonator loses; a higher value means lower energy loss.
IBM said additional losses as signals pass through the coupler wiring layers were also small. The results demonstrated the potential to implement complex connection structures.
Developing a dedicated 2-nanometer chip
Quantum error correction requires both software to detect errors and dedicated computing hardware. A “decoder” is an algorithm that analyzes information measured by a quantum computer to determine what errors have occurred.
IBM has improved Relay-BP, a decoder it unveiled in 2025. In a new study, the company found that error-correction performance was nearly identical for memory operations that store quantum information and measurement operations. IBM said the decoder algorithm’s measured performance now meets Starling’s requirements.
The next step is to run the algorithm in real time on an actual quantum computer. To do so, IBM is developing a dedicated application-specific integrated circuit (ASIC) using a 2-nanometer nanosheet process. An ASIC is a chip designed for a specific task; in Starling, it will rapidly analyze errors that occur during quantum operations.
Although the decoder algorithm meets the required performance, the complete real-time error-correction system is not yet finished.
Connecting two quantum processors
Scaling quantum computers requires connecting multiple processors. IBM is developing the l-coupler, a long-range connection device that links modules.
Recently, IBM successfully connected two Nighthawk processors using four l-couplers. The average error rate measured during the connection was 1%, with the best result at 0.7%.
IBM used high-quality coaxial cables with magnetic shielding. Compared with earlier experiments, the raw error rate was cut by about half. The company highlighted the ability to achieve consistent performance even when the connection devices were installed repeatedly.
Starling will require more than 100 l-couplers per module. The target error rate is 0.1%, which is 10 times lower than the current average of 1%. A key challenge in developing Starling is to sharply increase the number of connection devices while also reducing their error rate.
Cooling systems go modular, too
Quantum processors need a cryogenic environment to operate reliably. This year, IBM unveiled a new modular cryostat designed to connect multiple quantum processors.
Instead of the conventional cylindrical shape, the system uses a rectangular design so that cooling units can be connected side by side to scale up the system. The cooling engine, vacuum outer wall, and shielding and wiring structures have also been separated to improve stability when multiple units are assembled.
Dedicated passages between cooling units allow l-couplers to pass through. The wiring has also been improved. According to IBM, each section of the cooling system can accommodate up to about 1.54 kilometers of wiring. Nighthawk r2 requires about 1.38 kilometers, while its successor, r3, is expected to need about 6.18 kilometers.
IBM increased wiring density by replacing conventional coaxial cables with flexible wiring and repeatedly refining the design. As of November 2026, two Nighthawk r2 processors connected by l-couplers are being cooled inside the new modular system. The measured l-coupler quality factor is about 1 million to 2 million.
Starling is ultimately intended to connect as many as 12 cooling modules. IBM is also moving control chips inside the cryogenic system.
Today, quantum computers generally use control equipment at room temperature to send signals that manipulate qubits. This requires extensive wiring and can also introduce noise. IBM has developed control ASICs that operate in cryogenic environments.
In an earlier experiment, an ASIC controlled about half of the two-qubit gates on a Heron processor. The latest ASIC achieved gate performance equal to or better than that of room-temperature control equipment. IBM plans to build a modular real-time control system combining CPUs, FPGAs, and ASICs.
Starling targeted for 2029; large-scale integration remains the challenge
IBM’s quantum-computing roadmap is being pursued in stages. The company plans to develop Kookaburra, a modular processor combining quantum memory and a logical processing unit, in 2026; follow it with Cockatoo, which connects multiple modules, in 2027; and build Starling in 2029.
Starling is intended to be a fault-tolerant system capable of performing 100 million quantum operations using 200 logical qubits. Achieving this will require further reductions in the error rates of individual processors and reliable operation of a large number of connection devices. Real-time error correction, cryogenic control, and a large-scale cooling system will also need to be integrated into one machine.
IBM cited validation of c-coupler technology, a reduction in the number of Josephson junctions, achievement of the required decoder algorithm performance, connections between processors, and development of modular cooling and control technologies as key results in its announcement.
Research is also continuing on improvements to the logical processing unit and reductions in the additional resources needed for magic-state injection. Magic-state injection is a key technique for implementing a range of operations in an error-corrected quantum computer.
IBM said Starling’s basic architecture remains unchanged and that research to date supports its development direction. Whether the company meets its 2029 target will depend on its ability to integrate the individual technologies into a large-scale system and operate it reliably.